The present invention relates to a thin film semiconductor device and a liquid crystal display unit, and fabrication methods thereof. In particular, the present invention concerns a gate interconnection structure and a light shield structure for thin film transistors integrated on a thin film semiconductor.
Thin film semiconductors, on each of which thin film transistors and pixel electrodes are integrated, are being widely used for substrates for driving liquid crystal display units. In particular, a thin film semiconductor device built in a liquid crystal display unit for a projector is essential to have a light shield structure for shielding thin film transistors from intensive light coming from a liquid source of the projector. One example of such a liquid crystal display unit is shown in FIG. 5. As shown in this figure, the liquid crystal display unit uses a thin film transistor for driving each pixel electrode 8. The thin film transistor is typically composed of a high temperature polysilicon TFT; however, it may be composed of a low temperature polysilicon TFT or an amorphous silicon TFT. The liquid crystal display unit shown in the figure is disclosed, for example, in Japanese Patent Laid-open No. Hei 2000-131716. As shown in the figure, the liquid crystal display unit includes a substrate 1 (quartz for supporting TFTs) having TFTs 7 as pixel transistors and a counter substrate 2, with liquid crystal 3 held between the substrate 1 and the counter substrate 2. The counter substrate 2 has a counter electrode 6.
Referring to FIG. 5, the substrate 1 has a pixel electrode 8 in an upper layer portion, and a TFT (thin film transistor, which has a top gate structure herein) in a lower layer portion. The TFT 7 is used as a switching element for driving the pixel electrode 8. The TFT 7 has, as an active layer, a semiconductor thin film 10 which is made from first layer polysilicon. A gate electrode G is formed on the semiconductor thin film 10 via a gate insulating film 11 made from SiO2. The gate electrode G is made from second layer polysilicon. The TFT 7 has a source region S and a drain region D on both sides of the gate electrode G. LDD regions 71 and 72 are formed at end portions of the source and drain regions, respectively. Extraction electrodes 12A and 12B are connected to the source region S and the drain region D, respectively. Each of the extraction electrodes 12A and 12B is made from an aluminum based material such as aluminum. The extraction electrode 12A is electrically connected to the source region S of the TFT 7 via a contact hole SCN, and the extraction electrode 12B is electrically connected to the drain region D of the TFT 7 via a contact hole DCN.
The semiconductor thin film 10 includes an auxiliary capacitance (Cs) 13. The auxiliary capacitance (Cs) 13 is formed by holding a dielectric film made from, for example, SiO2 forming the gate insulating film 11 between the first layer polysilicon forming the semiconductor thin film 10, that is, the TFT 7, and the second layer polysilicon forming a semiconductor thin film 14, that is, the gate electrode G.
Light shield layers 4M and 4P are formed in an intermediate layer portion between the upper layer portion having the pixel electrode 8 and the lower layer portion having the TFT 7. The light shield layers 4M and 4P are located on the counter substrate 2 side with respect to the TFT 7, that is, on the light coming side, and therefore, they are called xe2x80x9cupper side light shield layersxe2x80x9d. That is to say, the upper side light shield layers herein are composed of the mask shield layer 4M and the pad shield layer 4P. With the aid of the two upper side light shield layers (mask shield layer 4M and pad shield layer 4P) and the extraction electrodes 12A and 12B (each of which is made from aluminum herein) overlapped to the upper side light shield layers, the overall pixel region except for a pixel opening is shielded from light coming from the counter substrate 2 side. Each of the mask shield layer 4M and the pad shield layer 4P is made from a conductive material, for example, a metal such as Ti. The mask shield layer 4M is continuously patterned along the row direction (cross direction) of the pixels, and shields the TFT at least partially from external light. The pad shield layer 4P is patterned discretely for each pixel, and contributes to the contact with the pixel electrode 8. To be more specific, the pixel electrode 8 is connected to the pad shield layer 4P via contact hole PCN. The pad shield layer 4P is connected to the extraction electrode 12B via a contact hole JCN. The extraction electrode 12B is, as described above, connected to the drain region D of the TFT 7 via the contact hole DCN. By providing the mask shield layer 4M and the pad shield layer 4P and the extraction electrodes 12A and 12B overlapped to the shield layers 4M and 4P, the overall pixel region except for the pixel opening can be shielded from light coming from the counter substrate side.
On the other hand, a light shield layer 5 is formed on a portion, opposed to the counter substrate 2 side, of the pixel transistor portion. This light shield layer 5 is called xe2x80x9clower light shield layerxe2x80x9d. At least the end portions of the source and drain of the pixel transistor 7, and the LDD regions 71 and 72 are formed at the end portions of the source and drain thus shielded from external light. In general, the lower light shield layer 5 is made from a silicide of a refractory metal, such as WSi and has a thickness of 200 nm.
To satisfy recent strong demands toward higher luminance of a liquid crystal projector, the liquid crystal panel of the type shown in FIG. 5 has been required to be improved in terms of its transmittance. At the same time, the liquid crystal panel shown in FIG. 5 has been required to keep a high image quality even under a condition with a large quantity of light coming from a light source for a projector. To meet these market requirements for the liquid crystal panel of the type shown in FIG. 5, there have been adopted a method (1) of improving the transmittance by increasing the pixel opening rate, and a method (2) of keeping a high image quality by increasing the area of an auxiliary capacitance (Cs). The methods (1) and (2), however, are essentially inconsistent with each other. Namely, if the auxiliary capacitance (Cs) is increased, the pixel opening rate is reduced. The reason why the methods (1) and (2) have been simultaneously adopted is due to the fact that there has been a margin of the layout of pixels. However, along with tendency toward higher definition of a liquid crystal projector, it has been difficult to realize the layout of pixels with such a margin, and it has become impossible to achieve higher pixel opening rate on the basis of the related art pixel structure.
FIG. 6 is a schematic plan view of the prior art liquid crystal display unit shown in FIG. 5, particularly, one pixel region of the liquid crystal display unit. As shown in the figure, the liquid crystal display unit includes a plurality of signal interconnections 12 and gate interconnections crossing the signal interconnections 12. Pixels are provided at crossing points between the signal interconnections extending to column direction (longitudinal direction) and the gate interconnections extending in the row direction (cross direction). As described above, the pixel includes the pixel electrode, the thin film transistor for driving the pixel electrode, and the light shield band (light shield layer) for shielding the thin film transistor from external light. The thin film transistor has, as the active layer, the semiconductor thin film 10. The source region of the semiconductor thin film 10 is connected to the signal interconnection 12 via the contact hole SCN; the drain region thereof is connected to the pixel electrode (not shown) via the contact hole DCN; and the gate electrode G thereof is formed as part of the gate interconnection. In addition, the gate interconnection is formed of the semiconductor thin film (made from second layer polysilicon) 14 different from the semiconductor thin film (made from first layer polysilicon) 10. The pixel also includes the auxiliary capacitance 13. The auxiliary capacitance 13 has such a stacked structure that the dielectric thin film being the same as the gate insulating film is held between the semiconductor thin film (first layer polysilicon) 10 and the semiconductor thin film (second layer polysilicon) 14. The semiconductor thin film 10 forming the lower electrode of the auxiliary capacitance 13 exhibits the same potential as that of the drain of the thin film transistor, and the semiconductor thin film 14 forming the upper electrode of the auxiliary capacitance 13 is connected to the upper side extraction electrode (not shown) made from aluminum via a contact hole CCN. The extraction electrode is further connected to the upper side mask shield layer via a contact hole MCN. The pixel electrode (not shown) is connected to the drain region D of the thin film transistor via the contact holes PCN, JCN and DCN. As shown in the figure, the gate electrode G is formed of the semiconductor thin film 14 (second layer polysilicon) which extends in the cross direction, to form the gate interconnection. Part of the semiconductor thin film 14, which is taken as the upper electrode of the auxiliary capacitance 13, exhibits a potential different from that of the gate interconnection. Accordingly, although both the gate interconnection and the upper electrode of the auxiliary capacitance 13 are formed of the same semiconductor thin film 14, they are required to be electrically separated to each other with a specific gap (GAP) put therebetween. That is to say, in this pixel structure, since the gate interconnection and the upper electrode of the auxiliary capacitance 13 are disposed in parallel to each other, the gap (GAP) must be provided therebetween, with a result that the pixel opening rate is reduced. To improve the pixel operating rate, as is easily understood, it is effective to form the gate interconnection and the upper electrode of the auxiliary capacitance 13 as separate layers; however, the prior art structure shown in FIG. 6 has failed to examine such a layout of the gate interconnection and the upper electrode of the auxiliary capacitance 13.
FIG. 7 is a graph showing a relationship between a pixel opening rate and the area of the auxiliary capacitance (Cs) in the prior art structure shown in FIG. 6. As the pixel opening rate is increased, the area of the auxiliary capacitance is sacrificed and is significantly reduced. This is because the gate interconnection and the upper electrode of the auxiliary capacitance (auxiliary capacitance interconnection) are formed of the same layer and are disposed in parallel to each other. Such a parallel layout of the gate interconnection and the auxiliary capacitance interconnection makes it difficult to improve the pixel opening rate while ensuring the area of the auxiliary capacitance.
An object of the present invention is to improve a pixel opening rate of a thin film semiconductor device used as a drive substrate of an active matrix type liquid crystal display unit.
To achieve the above object, according to the present invention, there is provided a thin film semiconductor device including: a plurality of signal interconnections and a plurality of gate interconnections crossing the signal interconnections, and pixels disposed at crossing points between the signal and gate interconnections, the signal and gate interconnections and the pixels being provided on an insulating substrate; wherein each of the pixels includes at least a pixel electrode, a thin film transistor for driving the pixel electrode, and a light shield band for shielding the thin film transistor from external light; and a source of the thin film transistor is connected to one of the signal interconnections, a drain of the thin film transistor is connected to the pixel electrode, and a gate electrode of the thin film transistor is connected to one of the gate interconnections. This thin film semiconductor device is characterized in that the light shield band is formed of a first conductive layer, and at least part of the light shield band is used as the gate interconnection; the gate electrode is formed of a second conductive layer different from the first conductive layer; and the first conductive layer used for the gate interconnection is electrically connected to the second conductive layer forming the gate electrode within each pixel region.
Preferably, the second conductive layer forming the gate electrodes is separated from each other for each pixel region, and each of the separated parts of the second conductive layer is electrically connected to the first conductive layer used for the gate interconnection in each pixel region.
Preferably, the first conductive layer forming the gate interconnection is separated from each other for each pixel region, and each of the separated parts of the first conductive layer is electrically connected to the second conductive layer forming the gate electrode within each pixel region.
Preferably, the light shield band is composed of two conductive layers for shielding the thin film transistor from above and below, and one of the two conductive layers is used as the first conductive layer for the gate interconnection.
Preferably, the light shield band is composed of a single conductive layer for shielding the thin film transistor from either above or below, and the single conductive layer is used as the first conductive layer for the gate interconnection.
Preferably, each of the pixels includes an auxiliary capacitance composed of a dielectric substance held between a pair of upper and lower electrodes in order to hold signal charges written from the signal interconnection into the pixel electrode via the thin film transistor; and one of the pair of upper and lower electrodes is formed of the same layer as the second conductive layer forming the gate electrode.
With these configurations, the light shield band for shielding the thin film transistor from external light is formed of the first conductive layer, and at least part of the light shield band is used as the gate interconnection. On the other hand, the gate electrode is formed of the second conductive layer different from the first conductive layer, and is electrically connected to the light shield band within each pixel region. By making use of the light shield layer as the gate interconnection as described above, it is not required to form the gate interconnection and the auxiliary capacitance interconnection with the same layer. For example, by using the lower light shield layer as the gate interconnection, the auxiliary capacitance interconnection formed of the same layer as that forming the gate electrode can be overlapped on the gate interconnection. Since it is not required to ensure the gap (GAP) between the gate interconnection and the auxiliary capacitance interconnection which are made from the same layer, the pixel opening rate can be correspondingly improved.